The invention relates to a digital-to-analog converter for converting a digital signal having a word length n into an analog signal, comprising
a series arrangement of a first and a second integrating circuit each having an input and output and a control signal input, the output of the first integrating circuit coupled to the input of the second integrating circuit, each of the the first and second integrating circuits comprising a first and a second amplifier stage, respectively, each having an inverting and non-inverting input and an output and a first and second capacitors, respectively, coupled between the inverting input and the output of the first and second amplifier stages, respectively, the first and the second integrating circuit being adapted to perform an integration step under the influence of a control signal applied to the control signal input,
a control unit having a first and a second output coupled to the control signal input of the first and the second integrating circuit, respectively, said control unit being adapted to supply, in this order, a first control signal at its first output, a second control signal at its second output, a third control signal at its first output and a fourth control signal at its second output.
A converter of this type is known from the published Japanese Patent Application (kokai) No. 59-8427 and is intended to convert an n-bit digital signal. The integrating circuits in the known converter are in the form of analog integrators.
The known converter is intended to convert 16-bit digital signals into analog signals and it operates as follows. Under the influence of the first control signal the first integrating circuit performs, M1 times an integration step so that a first value is derived which is proportional to 2.sup.8 Vref, in which Vref is a reference value. Subsequently the second integrating circuit is activated M2 times by the second control signal so that an analog signal, which is proportional to MSB.2.sup.8 Vref, is produced at the output of the second circuit, in which MSB is equal to the value of the binary number of the eight most significant bits of the 16-bit digital signal. Subsequently the output of the first integrating circuit is brought to an initial level (reset to zero in this case) under the influence of a reset signal of the control unit. Subsequently the first circuit performs M3 integration steps under the influence of the third control signal so that a value proportional to Vref is derived. The second circuit is then activated M4 times by the fourth control signal. An analog output signal is now produced which is proportional to (MSB.2.sup.8 +LSB)Vref in which LSB is equal to the value of the binary number of the eight least significant bits of the 16-bit digital signal. The known converter appears to have a disturbing offset component in the analog output signal.